1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to delay line circuits.
2. Description of the Related Art
In many complex digital systems, there often exists a need for providing delay lines. Delay lines may be useful for such tasks as providing a phase delay to align the edges of a clock signal or providing a delay for a signal in order to synchronize it with another signal. Delay lines may be particularly useful in areas where multiple signals encountering differing propagation delays on their respective signal paths must be synchronized.
Delay lines are used in a wide variety of applications, and have many different implementations. Integrated circuits may include delay lines that are implemented in the silicon die. The performance of delay lines implemented on a silicon die may depend on the silicon technology used. One silicon technology that is commonly used today is known as silicon-on-insulator (SOI). FIG. 1 illustrates an SOI transistor. In the embodiment shown, insulating material is embedded in the body of the silicon. The presence of the insulator electrically decouples the portion of the body immediately beneath the transistor terminals from the remainder of the body that is coupled to electrical ground. Thus, the voltage in the body immediately beneath the transistor terminals floats due to capacitance between itself and the portion of the body coupled to ground.
A key objective in implementing a delay line is the ability of the delay line to provide a consistent and predictable delay time. However, this objective may be difficult to achieve in a delay line implemented using SOI technology. Due to the floating voltage of the body immediately beneath the transistor terminals and the capacitance between that portion of the body and the portion that is electrically coupled to ground, hysterisis may develop, particularly if the delay line is inactive for a certain amount of time. This hysterisis, when multiplied over the number of transistors used to implement the delay line, can cause a significant variation and inconsistency in the delay time provided by the delay line.